
Analog circuit design : fractional-N synthesizers, design for robustness, line and bus drivers
Analog circuit design : fractional-N synthesizers, design for robustness, line and bus drivers | |
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Original Title | Analog circuit design : fractional-N synthesizers, design for robustness, line and bus drivers |
Author | Workshop of Advances in Analogue Circuit Design (12th : 2003 : Graz, Austria), Roermund, Arthur H. M. van, Steyaert, Michiel, 1959-, Huijsing, Johan H., 1938- |
Publication date |
2003 |
Topics | Linear integrated circuits, Frequency synthesizers, Electronic circuit design |
Publisher | Boston : Kluwer Academic Publishers |
Collection | folkscanomy_miscellaneous, folkscanomy, additional_collections |
Language | English |
Book Type | EBook |
Material Type | Book |
File Type | |
Downloadable | Yes |
Support | Mobile, Desktop, Tablet |
Scan Quality: | Best No watermark |
PDF Quality: | Good |
Availability | Yes |
Price | 0.00 |
Submitted By | Sketch the Cow |
Submit Date | |
Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus DriversAuthor: Arthur van Roermund, Michiel Steyaert, Johan H. Huijsing Published by Springer US ISBN: 978-1-4020-7559-9 DOI: 10.1007/b105729Table of Contents:Practical Design Aspects in Fractional-N Frequency Synthesis Design and Simulation of Fractional-N Frequency Synthesizers Monolithic CMOS Fractional-N Frequency Synthesizer Design for High Spectral Purity A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser With 35Hz Frequency Step and Quantization Noise Compensation Implementation Aspects of Fractional-N Techniques in Cellular Handsets Fractional-N Phase Locked Loops and It’s Application in the GSM System ESD for Analogue Circuit Design ESD in Smart Power Processes RF-ESD Co-Design for High Performance CMOS LNAs Improvement of System Robustness Through EMC Optimization Robustness in Analog Design Minimizing Undesired Coupling and Interaction in Mixed Signal ICs. Looking to/for Low Power ADSL Drivers in the DSLAM. Class-AB Low-Distortion drivers for ADSL Class D Self-Oscillating Line Drivers Class G/H Line Drivers for xDSL The USB 2.0 Physical Layer: Standard and Implementation Backplane TransceiversRev. and extended tutorials presented at the 12th Workshop of Advances in Analog Circuit Design (AACD) held at 15-17 April 2003, in Graz, AustriaIncludes bibliographical references and index |