Advances in computer systems architecture : 9th Asia Pacific conference, ACSAC 2004, Beijing, China, September
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Author: ACSAC 2004 (2004 : Beijing, China), Yew, Pen-Chung, 1950-, Xue, Jingling, 1962-
Added by: sketch
Added Date: 2015-12-29
Language: eng
Subjects: Computer architecture
Publishers: Berlin ; New York : Springer
Collections: journals contributions, journals
ISBN Number: 3540230033
Pages Count: 300
PPI Count: 300
PDF Count: 1
Total Size: 307.81 MB
PDF Size: 7.61 MB
Extensions: djvu, gif, pdf, gz, zip, torrent, log, mrc
Edition: 1. ed.
Downloads: 626
Views: 676
Total Files: 18
Media Type: texts
Total Files: 5
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Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings
Author: Pen-Chung Yew, Jingling Xue
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-23003-8
DOI: 10.1007/b100354
Table of Contents:
Includes bibliographical references and index
Author: Pen-Chung Yew, Jingling Xue
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-23003-8
DOI: 10.1007/b100354
Table of Contents:
- Some Real Observations on Virtual Machines
- Replica Victim Caching to Improve Reliability of In-Cache Replication
- Efficient Victim Mechanism on Sector Cache Organization
- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy
- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures
- A Configurable System-on-Chip Architecture for Embedded Devices
- An Auto-adaptative Reconfigurable Architecture for the Control
- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory
- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System
- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP
- TengYue-1: A High Performance Embedded SoC
- A Fault-Tolerant Single-Chip Multiprocessor
- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization
- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption
- Dynamic Reallocation of Functional Units in Superscalar Processors
- Multiple-Dimension Scalable Adaptive Stream Architecture
- Impact of Register-Cache Bandwidth Variation on Processor Performance
- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling
- Continuous Adaptive Object-Code Re-optimization Framework
Includes bibliographical references and index
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