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Correct hardware design and verification methods [electronic resource] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003 : proceedings

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Correct hardware design and verification methods [electronic resource] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003 : proceedings
Original Title Correct hardware design and verification methods [electronic resource] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003 : proceedings
Author CHARME 2003 (2003 : L’Aquila, Italy), Geist, Daniel, 1961-, Tronci, Enrico, 1961-, SpringerLink (Online service)
Publication date

Topics Integrated circuits, Integrated circuits
Publisher Berlin , Hong Kong : Springer-Verlag
Collection folkscanomy_miscellaneous, folkscanomy, additional_collections
Language English
Book Type EBook
Material Type Book
File Type PDF
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Correct Hardware Design and Verification Methods: 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003. Proceedings
Author: Daniel Geist, Enrico Tronci
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-20363-6
DOI: 10.1007/b93958

Table of Contents:

  • What Is beyond the RTL Horizon for Microprocessor and System Design?
  • The Charme of Abstract Entities
  • The PSL/Sugar Specification Language A Language for all Seasons
  • Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular
  • Predicate Abstraction with Minimum Predicates
  • Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning
  • Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP
  • A Hazards-Based Correctness Statement for Pipelined Circuits
  • Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
  • On Complementing Nondeterministic BĂĽchi Automata
  • Coverage Metrics for Formal Verification
  • “More Deterministic” vs. “Smaller” BĂĽchi Automata for Efficient LTL Model Checking
  • An Optimized Symbolic Bounded Model Checking Engine
  • Constrained Symbolic Simulation with Mathematica and ACL2
  • Semi-formal Verification of Memory Systems by Symbolic Simulation
  • CTL May Be Ambiguous When Model Checking Moore Machines
  • Reasoning about GSTE Assertion Graphs
  • Towards Diagrammability and Efficiency in Event Sequence Languages
  • Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving
  • On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking

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Caption title , description based on screen of 2005-03-02

Includes bibliographical references

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