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Advanced verification techniques [electronic resource] : a systemC based approach for successful tapeout | Singh, Leena, 1971-, Drucker, Leonard, Khann, Neyaz

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Advanced verification techniques [electronic resource] : a systemC based approach for successful tapeout

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Author: Singh, Leena, 1971-, Drucker, Leonard, Khann, Neyaz

Added by: sketch

Added Date: 2015-12-30

Publication Date: 2004

Language: eng

Subjects: Integrated circuits, TECHNOLOGY & ENGINEERING, TECHNOLOGY & ENGINEERING, Integrated circuits

Publishers: Boston : Kluwer Academic Publishers

Collections: folkscanomy miscellaneous, folkscanomy, additional collections

ISBN Number: 1402080298, 9781402080296, 9781402076725, 140207672X

Pages Count: 300

PPI Count: 300

PDF Count: 1

Total Size: 139.98 MB

PDF Size: 10.34 MB

Extensions: djvu, gif, pdf, gz, zip, torrent, log, mrc

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Downloads: 814

Views: 864

Total Files: 18

Media Type: texts

Description

Advanced Verification Techniques: A SystemC Based Approach for Successful Tapeout
Author: Leena Singh, Leonard Drucker, Neyaz Khan
Published by Springer US
ISBN: 978-1-4020-7672-5
DOI: 10.1007/b105272

Table of Contents:

  • Introduction
  • Verification Process
  • Using SCV for Verification
  • Functional Verification Testplan
  • Testbench Concepts using SystemC
  • Verification Methodology
  • Regression/Setup and Run
  • Functional Coverage
  • Dynamic Memory Modeling
  • Post Synthesis Gate Simulation

Includes bibliographical references (pages 371-372) and index
Introduction -- Verification Process -- Using SCV for Verification -- Functional Verification Testplan -- Testbench Concepts using SystemC -- Verification Methodology.-Regression/Setup and Run -- Functional Coverage -- Dynamic Memory Modeling -- Post Synthesis Gate Simulation -- Appendices
"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."--Stuart Swan
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